Staging
v0.8.1
v0.8.1
swh:1:snp:a902887e4be9191b7c6c4406aa06b31c1ce2c7cc
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- v3.9-rc8
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- v3.19-rc1
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- v3.18-rc7
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- v3.16-rc1
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- v3.14-rc8
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- v3.10
- v3.1-rc9
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- v3.0-rc1
- v3.0
- v2.6.39-rc7
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- v2.6.38-rc1
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- v2.6.32
- v2.6.31-rc9
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- v2.6.31-rc1
- v2.6.31
- v2.6.30-rc8
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- v2.6.30-rc1
- v2.6.30
- v2.6.29-rc8
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- v2.6.29-rc1
- v2.6.29
- v2.6.28-rc9
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- v2.6.28-rc1
- v2.6.28
- v2.6.27-rc9
- v2.6.27-rc8
- v2.6.27-rc7
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- v2.6.27-rc1
- v2.6.27
- v2.6.26-rc9
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- v2.6.26-rc1
- v2.6.26
- v2.6.25-rc9
- v2.6.25-rc8
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- v2.6.25-rc1
- v2.6.25
- v2.6.24-rc8
- v2.6.24-rc7
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- v2.6.24-rc3
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- v2.6.24-rc1
- v2.6.24
- v2.6.23-rc9
- v2.6.23-rc8
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- v2.6.23-rc1
- v2.6.23
- v2.6.22-rc7
- v2.6.22-rc6
- v2.6.22-rc5
- v2.6.22-rc4
- v2.6.22-rc3
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- v2.6.22-rc1
- v2.6.22
- v2.6.21-rc7
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- v2.6.21-rc1
- v2.6.21
- v2.6.20-rc7
- v2.6.20-rc6
- v2.6.20-rc5
- v2.6.20-rc4
- v2.6.20-rc3
- v2.6.20-rc2
- v2.6.20-rc1
- v2.6.20
- v2.6.19-rc6
- v2.6.19-rc5
- v2.6.19-rc4
- v2.6.19-rc3
- v2.6.19-rc2
- v2.6.19-rc1
- v2.6.19
- v2.6.18-rc7
- v2.6.18-rc6
- v2.6.18-rc5
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- v2.6.18-rc1
- v2.6.18
- v2.6.17-rc6
- v2.6.17-rc5
- v2.6.17-rc4
- v2.6.17-rc3
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- v2.6.17-rc1
- v2.6.17
- v2.6.16-rc6
- v2.6.16-rc5
- v2.6.16-rc4
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- v2.6.16-rc1
- v2.6.16
- v2.6.15-rc7
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- v2.6.15-rc1
- v2.6.15
- v2.6.14-rc5
- v2.6.14-rc4
- v2.6.14-rc3
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Tip revision: 9e1ff307c779ce1f0f810c7ecce3d95bbae40896 authored by Linus Torvalds on 03 October 2021, 21:08:47 UTC
Linux 5.15-rc4
Linux 5.15-rc4
Tip revision: 9e1ff30
spi-fsl-spi.h
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Freescale SPI controller driver.
*
* Maintainer: Kumar Gala
*
* Copyright (C) 2006 Polycom, Inc.
* Copyright 2010 Freescale Semiconductor, Inc.
*
* CPM SPI and QE buffer descriptors mode support:
* Copyright (c) 2009 MontaVista Software, Inc.
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
*
* GRLIB support:
* Copyright (c) 2012 Aeroflex Gaisler AB.
* Author: Andreas Larsson <andreas@gaisler.com>
*/
#ifndef __SPI_FSL_SPI_H__
#define __SPI_FSL_SPI_H__
/* SPI Controller registers */
struct fsl_spi_reg {
__be32 cap; /* TYPE_GRLIB specific */
u8 res1[0x1C];
__be32 mode;
__be32 event;
__be32 mask;
__be32 command;
__be32 transmit;
__be32 receive;
__be32 slvsel; /* TYPE_GRLIB specific */
};
/* SPI Controller mode register definitions */
#define SPMODE_LOOP (1 << 30)
#define SPMODE_CI_INACTIVEHIGH (1 << 29)
#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
#define SPMODE_DIV16 (1 << 27)
#define SPMODE_REV (1 << 26)
#define SPMODE_MS (1 << 25)
#define SPMODE_ENABLE (1 << 24)
#define SPMODE_LEN(x) ((x) << 20)
#define SPMODE_PM(x) ((x) << 16)
#define SPMODE_OP (1 << 14)
#define SPMODE_CG(x) ((x) << 7)
/* TYPE_GRLIB SPI Controller capability register definitions */
#define SPCAP_SSEN(x) (((x) >> 16) & 0x1)
#define SPCAP_SSSZ(x) (((x) >> 24) & 0xff)
#define SPCAP_MAXWLEN(x) (((x) >> 20) & 0xf)
/*
* Default for SPI Mode:
* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
*/
#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
/* SPIE register values */
#define SPIE_NE 0x00000200 /* Not empty */
#define SPIE_NF 0x00000100 /* Not full */
/* SPIM register values */
#define SPIM_NE 0x00000200 /* Not empty */
#define SPIM_NF 0x00000100 /* Not full */
#endif /* __SPI_FSL_SPI_H__ */