Staging
v0.8.1
v0.8.1
swh:1:snp:a902887e4be9191b7c6c4406aa06b31c1ce2c7cc
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- v3.9-rc8
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- v3.19-rc1
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- v3.18-rc7
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- v3.16-rc1
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- v3.14-rc8
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- v3.10
- v3.1-rc9
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- v3.0-rc1
- v3.0
- v2.6.39-rc7
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- v2.6.38-rc1
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- v2.6.32
- v2.6.31-rc9
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- v2.6.31-rc1
- v2.6.31
- v2.6.30-rc8
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- v2.6.30-rc1
- v2.6.30
- v2.6.29-rc8
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- v2.6.29-rc1
- v2.6.29
- v2.6.28-rc9
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- v2.6.28-rc1
- v2.6.28
- v2.6.27-rc9
- v2.6.27-rc8
- v2.6.27-rc7
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- v2.6.27-rc1
- v2.6.27
- v2.6.26-rc9
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- v2.6.26-rc1
- v2.6.26
- v2.6.25-rc9
- v2.6.25-rc8
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- v2.6.25-rc1
- v2.6.25
- v2.6.24-rc8
- v2.6.24-rc7
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- v2.6.24-rc3
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- v2.6.24-rc1
- v2.6.24
- v2.6.23-rc9
- v2.6.23-rc8
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- v2.6.23-rc1
- v2.6.23
- v2.6.22-rc7
- v2.6.22-rc6
- v2.6.22-rc5
- v2.6.22-rc4
- v2.6.22-rc3
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- v2.6.22-rc1
- v2.6.22
- v2.6.21-rc7
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- v2.6.21-rc1
- v2.6.21
- v2.6.20-rc7
- v2.6.20-rc6
- v2.6.20-rc5
- v2.6.20-rc4
- v2.6.20-rc3
- v2.6.20-rc2
- v2.6.20-rc1
- v2.6.20
- v2.6.19-rc6
- v2.6.19-rc5
- v2.6.19-rc4
- v2.6.19-rc3
- v2.6.19-rc2
- v2.6.19-rc1
- v2.6.19
- v2.6.18-rc7
- v2.6.18-rc6
- v2.6.18-rc5
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- v2.6.18-rc1
- v2.6.18
- v2.6.17-rc6
- v2.6.17-rc5
- v2.6.17-rc4
- v2.6.17-rc3
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- v2.6.17-rc1
- v2.6.17
- v2.6.16-rc6
- v2.6.16-rc5
- v2.6.16-rc4
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- v2.6.16-rc1
- v2.6.16
- v2.6.15-rc7
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- v2.6.15-rc1
- v2.6.15
- v2.6.14-rc5
- v2.6.14-rc4
- v2.6.14-rc3
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Tip revision: 2ddcca36c8bcfa251724fe342c8327451988be0d authored by Linus Torvalds on 03 May 2008, 18:59:44 UTC
Linux 2.6.26-rc1
Linux 2.6.26-rc1
Tip revision: 2ddcca3
DMA-attributes.txt
DMA attributes
==============
This document describes the semantics of the DMA attributes that are
defined in linux/dma-attrs.h.
DMA_ATTR_WRITE_BARRIER
----------------------
DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA. DMA
to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
all pending DMA writes to complete, and thus provides a mechanism to
strictly order DMA from a device across all intervening busses and
bridges. This barrier is not specific to a particular type of
interconnect, it applies to the system as a whole, and so its
implementation must account for the idiosyncracies of the system all
the way from the DMA device to memory.
As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
useful, suppose that a device does a DMA write to indicate that data is
ready and available in memory. The DMA of the "completion indication"
could race with data DMA. Mapping the memory used for completion
indications with DMA_ATTR_WRITE_BARRIER would prevent the race.