Staging
v0.8.1
https://github.com/torvalds/linux
Revision 9448732f6c9ef4932b226056338d1084f3669752 authored by Sergei Shtylyov on 13 December 2006, 08:35:49 UTC, committed by Linus Torvalds on 13 December 2006, 17:05:55 UTC
Fix/remove bad/unused timing tables: HPT370/A 66 MHz tables weren't really
needed (the chips are not UltraATA/133 capable and shouldn't support 66 MHz
PCI) and had many modes over- and underclocked, HPT372 33 MHz table was in
fact for 66 MHz and 50 MHz table missed UltraDMA mode 6, HPT374 33 MHz table
was really for 50 MHz...  (Actually, HPT370/A 33 MHz tables also have issues.
e.g.  HPT370 has PIO modes 0/1 overlocked.)

There's also no need in the separate HPT374 tables because HPT372 timings
should be the same (and those tables has UltraDMA mode 6 which HPT374 supports
depending on HPT374_ALLOW_ATA133_6 #define)...

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
1 parent 836c006
Raw File
Tip revision: 9448732f6c9ef4932b226056338d1084f3669752 authored by Sergei Shtylyov on 13 December 2006, 08:35:49 UTC
[PATCH] ide: fix HPT37x timing tables
Tip revision: 9448732
mpc8xx.h
/* This is the single file included by all MPC8xx build options.
 * Since there are many different boards and no standard configuration,
 * we have a unique include file for each.  Rather than change every
 * file that has to include MPC8xx configuration, they all include
 * this one and the configuration switching is done here.
 */
#ifdef __KERNEL__
#ifndef __CONFIG_8xx_DEFS
#define __CONFIG_8xx_DEFS


#ifdef CONFIG_8xx

#ifdef CONFIG_MBX
#include <platforms/mbx.h>
#endif

#ifdef CONFIG_FADS
#include <platforms/fads.h>
#endif

#ifdef CONFIG_RPXLITE
#include <platforms/rpxlite.h>
#endif

#ifdef CONFIG_BSEIP
#include <platforms/bseip.h>
#endif

#ifdef CONFIG_RPXCLASSIC
#include <platforms/rpxclassic.h>
#endif

#if defined(CONFIG_TQM8xxL)
#include <platforms/tqm8xx.h>
#endif

#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
#include <platforms/ivms8.h>
#endif

#if defined(CONFIG_HERMES_PRO)
#include <platforms/hermes.h>
#endif

#if defined(CONFIG_IP860)
#include <platforms/ip860.h>
#endif

#if defined(CONFIG_LWMON)
#include <platforms/lwmon.h>
#endif

#if defined(CONFIG_PCU_E)
#include <platforms/pcu_e.h>
#endif

#if defined(CONFIG_CCM)
#include <platforms/ccm.h>
#endif

#if defined(CONFIG_LANTEC)
#include <platforms/lantec.h>
#endif

#if defined(CONFIG_MPC885ADS)
#include <platforms/mpc885ads.h>
#endif

/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
 * use the same memory map.
 */
#if 0
#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
#define	_IO_BASE PCI_ISA_IO_ADDR
#define	_ISA_MEM_BASE PCI_ISA_MEM_ADDR
#define PCI_DRAM_OFFSET 0x80000000
#else
#define _IO_BASE        0
#define _ISA_MEM_BASE   0
#define PCI_DRAM_OFFSET 0
#endif
#else
#if !defined(_IO_BASE)  /* defined in board specific header */
#define _IO_BASE        0
#endif
#define _ISA_MEM_BASE   0
#define PCI_DRAM_OFFSET 0
#endif

#ifndef __ASSEMBLY__
/* The "residual" data board information structure the boot loader
 * hands to us.
 */
extern unsigned char __res[];

struct pt_regs;

enum ppc_sys_devices {
	MPC8xx_CPM_FEC1,
	MPC8xx_CPM_FEC2,
	MPC8xx_CPM_I2C,
	MPC8xx_CPM_SCC1,
	MPC8xx_CPM_SCC2,
	MPC8xx_CPM_SCC3,
	MPC8xx_CPM_SCC4,
	MPC8xx_CPM_SPI,
	MPC8xx_CPM_MCC1,
	MPC8xx_CPM_MCC2,
	MPC8xx_CPM_SMC1,
	MPC8xx_CPM_SMC2,
	MPC8xx_CPM_USB,
	MPC8xx_MDIO_FEC,
	NUM_PPC_SYS_DEVS,
};

#define PPC_PIN_SIZE	(24 * 1024 * 1024)	/* 24Mbytes of data pinned */

#ifndef BOARD_CHIP_NAME
#define BOARD_CHIP_NAME ""
#endif

#endif /* !__ASSEMBLY__ */
#endif /* CONFIG_8xx */
#endif /* __CONFIG_8xx_DEFS */
#endif /* __KERNEL__ */
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