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Staging
v0.8.1
https://github.com/torvalds/linux
02 December 2023, 22:23:51 UTC
Revision 398e692fd5cecdd25d311b47bbae69f7bac3a3cb authored by Lennert Buytenhek on 31 March 2007, 11:03:20 UTC, committed by Russell King on 01 April 2007, 21:38:36 UTC 
[ARM] 4298/1: fix memory barriers for DMA coherent and SMP platforms
 
This patch:
- Switches mb/rmb/wmb back to being full-blown DMBs on ARM SMP systems,
  since mb/rmb/wmb are required to order Normal memory accesses as well.
- Enables the use of DMB and ISB on XSC3 (which is an ARMv5TE ISA core
  but conforms to the ARMv6 memory ordering model and supports the
  various ARMv6 barriers.)
- Makes DMA coherent platforms (only ixp23xx at the moment) map
  mb/rmb/wmb to dmb(), as on DMA coherent platforms, DMA consistent
  mappings are done as Normal mappings, which are weakly ordered.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: David Howells <dhowells@redhat.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent 9a4d93d
History
Tip revision: 398e692fd5cecdd25d311b47bbae69f7bac3a3cb authored by Lennert Buytenhek on 31 March 2007, 11:03:20 UTC
[ARM] 4298/1: fix memory barriers for DMA coherent and SMP platforms
Tip revision: 398e692
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