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v0.5.1
https://github.com/torvalds/linux
Revision 217874feed0d3a6543a6b7127782f4a08bffd731 authored by Gen FUKATSU on 30 September 2005, 15:09:17 UTC, committed by Russell King on 30 September 2005, 15:09:17 UTC
Patch from Gen FUKATSU

Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.

Signed-off-by: Gen Fukatsu
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent a06f546
History
Tip revision: 217874feed0d3a6543a6b7127782f4a08bffd731 authored by Gen FUKATSU on 30 September 2005, 15:09:17 UTC
[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S
Tip revision: 217874f
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