// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

conn_subsys: bus@5b000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;

	conn_axi_clk: clock-conn-axi {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <333333333>;
		clock-output-names = "conn_axi_clk";
	};

	conn_ahb_clk: clock-conn-ahb {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <166666666>;
		clock-output-names = "conn_ahb_clk";
	};

	conn_ipg_clk: clock-conn-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <83333333>;
		clock-output-names = "conn_ipg_clk";
	};

	usdhc1: mmc@5b010000 {
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x5b010000 0x10000>;
		clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
			 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
			 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "per", "ahb";
		power-domains = <&pd IMX_SC_R_SDHC_0>;
		status = "disabled";
	};

	usdhc2: mmc@5b020000 {
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x5b020000 0x10000>;
		clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
			 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
			 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "per", "ahb";
		power-domains = <&pd IMX_SC_R_SDHC_1>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		status = "disabled";
	};

	usdhc3: mmc@5b030000 {
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x5b030000 0x10000>;
		clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
			 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
			 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "per", "ahb";
		power-domains = <&pd IMX_SC_R_SDHC_2>;
		status = "disabled";
	};

	fec1: ethernet@5b040000 {
		reg = <0x5b040000 0x10000>;
		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
			 <&enet0_lpcg IMX_LPCG_CLK_2>,
			 <&enet0_lpcg IMX_LPCG_CLK_1>,
			 <&enet0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		power-domains = <&pd IMX_SC_R_ENET_0>;
		status = "disabled";
	};

	fec2: ethernet@5b050000 {
		reg = <0x5b050000 0x10000>;
		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
			 <&enet1_lpcg IMX_LPCG_CLK_2>,
			 <&enet1_lpcg IMX_LPCG_CLK_1>,
			 <&enet1_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		power-domains = <&pd IMX_SC_R_ENET_1>;
		status = "disabled";
	};

	/* LPCG clocks */
	sdhc0_lpcg: clock-controller@5b200000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b200000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>, <&conn_axi_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
				<IMX_LPCG_CLK_5>;
		clock-output-names = "sdhc0_lpcg_per_clk",
				     "sdhc0_lpcg_ipg_clk",
				     "sdhc0_lpcg_ahb_clk";
		power-domains = <&pd IMX_SC_R_SDHC_0>;
	};

	sdhc1_lpcg: clock-controller@5b210000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b210000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>, <&conn_axi_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
				<IMX_LPCG_CLK_5>;
		clock-output-names = "sdhc1_lpcg_per_clk",
				     "sdhc1_lpcg_ipg_clk",
				     "sdhc1_lpcg_ahb_clk";
		power-domains = <&pd IMX_SC_R_SDHC_1>;
	};

	sdhc2_lpcg: clock-controller@5b220000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b220000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>, <&conn_axi_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
				<IMX_LPCG_CLK_5>;
		clock-output-names = "sdhc2_lpcg_per_clk",
				     "sdhc2_lpcg_ipg_clk",
				     "sdhc2_lpcg_ahb_clk";
		power-domains = <&pd IMX_SC_R_SDHC_2>;
	};

	enet0_lpcg: clock-controller@5b230000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b230000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
			 <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
				<IMX_LPCG_CLK_5>;
		clock-output-names = "enet0_ipg_root_clk",
				     "enet0_tx_clk",
				     "enet0_ahb_clk",
				     "enet0_ipg_clk",
				     "enet0_ipg_s_clk";
		power-domains = <&pd IMX_SC_R_ENET_0>;
	};

	enet1_lpcg: clock-controller@5b240000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b240000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
			 <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
				<IMX_LPCG_CLK_5>;
		clock-output-names = "enet1_ipg_root_clk",
				     "enet1_tx_clk",
				     "enet1_ahb_clk",
				     "enet1_ipg_clk",
				     "enet1_ipg_s_clk";
		power-domains = <&pd IMX_SC_R_ENET_1>;
	};
};