Xilinx AXI VDMA engine, it does transfers between memory and video devices.
It can be configured to have one channel or two channels. If configured
as two channels, one is to transmit to the video device and another is
to receive from the video device.

Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
target devices. It can be configured to have one channel or two channels.
If configured as two channels, one is to transmit to the device and another
is to receive from the device.

Xilinx AXI CDMA engine, it does transfers between memory-mapped source
address and a memory-mapped destination address.

Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
target devices. It can be configured to have up to 16 independent transmit
and receive channels.

Required properties:
- compatible: Should be one of-
		"xlnx,axi-vdma-1.00.a"
		"xlnx,axi-dma-1.00.a"
		"xlnx,axi-cdma-1.00.a"
		"xlnx,axi-mcdma-1.00.a"
- #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain VDMA registers location and length.
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
- dma-channel child node: Should have at least one channel and can have up to
	two channels per device. This node specifies the properties of each
	DMA channel (see child node properties below).
- clocks: Input clock specifier. Refer to common clock bindings.
- clock-names: List of input clocks
	For VDMA:
	Required elements: "s_axi_lite_aclk"
	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
	For CDMA:
	Required elements: "s_axi_lite_aclk", "m_axi_aclk"
	For AXIDMA and MCDMA:
	Required elements: "s_axi_lite_aclk"
	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
			   "m_axi_sg_aclk"

Required properties for VDMA:
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.

Optional properties for AXI DMA and MCDMA:
- xlnx,sg-length-width: Should be set to the width in bits of the length
	register as configured in h/w. Takes values {8...26}. If the property
	is missing or invalid then the default value 23 is used. This is the
	maximum value that is supported by all IP versions.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
	It takes following values:
	{1}, flush both channels
	{2}, flush mm2s channel
	{3}, flush s2mm channel

Required child node properties:
- compatible:
	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
	"xlnx,axi-vdma-s2mm-channel".
	For CDMA: It should be "xlnx,axi-cdma-channel".
	For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
	or "xlnx,axi-dma-s2mm-channel".
- interrupts: Should contain per channel VDMA interrupts.
- xlnx,datawidth: Should contain the stream data width, take values
	{32,64...1024}.

Optional child node properties:
- xlnx,include-dre: Tells hardware is configured for Data
	Realignment Engine.
Optional child node properties for VDMA:
- xlnx,genlock-mode: Tells Genlock synchronization is
	enabled/disabled in hardware.
- xlnx,enable-vert-flip: Tells vertical flip is
	enabled/disabled in hardware(S2MM path).
Optional child node properties for MCDMA:
- dma-channels: Number of dma channels in child node.

Example:
++++++++

axi_vdma_0: axivdma@40030000 {
	compatible = "xlnx,axi-vdma-1.00.a";
	#dma_cells = <1>;
	reg = < 0x40030000 0x10000 >;
	dma-ranges = <0x00000000 0x00000000 0x40000000>;
	xlnx,num-fstores = <0x8>;
	xlnx,flush-fsync = <0x1>;
	xlnx,addrwidth = <0x20>;
	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
	dma-channel@40030000 {
		compatible = "xlnx,axi-vdma-mm2s-channel";
		interrupts = < 0 54 4 >;
		xlnx,datawidth = <0x40>;
	} ;
	dma-channel@40030030 {
		compatible = "xlnx,axi-vdma-s2mm-channel";
		interrupts = < 0 53 4 >;
		xlnx,datawidth = <0x40>;
	} ;
} ;


* DMA client

Required properties:
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
	where Channel ID is '0' for write/tx and '1' for read/rx
	channel. For MCMDA, MM2S channel(write/tx) ID start from
	'0' and is in [0-15] range. S2MM channel(read/rx) ID start
	from '16' and is in [16-31] range. These channels ID are
	fixed irrespective of IP configuration.

- dma-names: a list of DMA channel names, one per "dmas" entry

Example:
++++++++

vdmatest_0: vdmatest@0 {
	compatible ="xlnx,axi-vdma-test-1.00.a";
	dmas = <&axi_vdma_0 0
		&axi_vdma_0 1>;
	dma-names = "vdma0", "vdma1";
} ;